1. Field of the Invention
The present invention relates to a chopper type voltage comparator and an analog/digital converter.
2. Description of the Related Art
Since the signal read from a solid state imaging device is an analog value, the an analog/digital converter for converting this analog value into the a digital value is needed. Among the devices employed as this analog/digital converter in the prior art, there is the integral column type analog/digital converter.
In this integral column type analog/digital converter, a ramp wave output from a ramp wave generator and the read signal are input into a voltage comparator. Then, a counter that starts counting a clock pulse in synchronism with initiation of the ramp wave is provided at to latch the count value at the instance when the ramp voltage exceeds the read voltage and then output the count value as the digital value. The employed voltage comparator, is a chopper type voltage comparator using an inverter, or the like.
In a solid state imaging device, the analog/digital conversion must be executed for each individual pixels residing on a horizontal line. Therefore, the above number of voltage comparators must equal the number of pixels on one horizontal line. In this case, if the consumption power of an individual voltage comparator is large, the overall consumption power becomes immense.
In the chopper type voltage comparator using the inverter, when the input voltage of the inverter comes close to the operating-point voltage, both the PMOS and the NMOS in the inverter are turned ON and thus a shoot through current flows in the inverter. This shoot through current continues to flow while this ON state is maintained. This shoot through current acts as a factor to increase the consumption power of the chopper type voltage comparator and thus increases the overall consumption power of the analog/digital converter.
In order to prevent this, one may consider reducing the shoot through current by extending the channel lengths of the PMOS and the NMOS. In this case, however, since the gate capacitance of the inverter increases, the output gain of the analog/digital converter degrades with respect to the ramp wave.
The present invention has been made in view of the problem in the prior art, and it is an object of the present invention to provide a voltage comparator and an analog/digital converter using the same wherein power consumption is reduced from the prior art.
According to the chopper type voltage comparator of the present invention, instead of applying a constant bias voltage to the comparator, the bias voltage is varied in accordance with the ramp voltage during the comparing operation. Then, when ramp voltage becomes substantially equal to the input voltage, the bias voltage is made into the predetermined voltage value that can bring the comparator into its comparing operation state.
According to this operation, only a small quantity of bias current flows through the comparator in the period when the ramp voltage is small, whereas a sufficient bias current for enabling the comparator to perform a desired comparing operation flows when the ramp voltage becomes substantially equal to the input voltage.
In this manner, in the present invention, since the bias current is not constant but is gradually increased, total current that flows through the comparator can be reduced and also the consumption power can be reduced.
An example of the chopper type voltage comparator according to the present invention is exemplified in FIG. 1. As shown in FIG. 1, this chopper type voltage comparator 1 comprises an input capacitor C2, a bias capacitor C3, and a first differential amplifier OP1. This first differential amplifier OP1 has a first input terminal INP, a second input terminal INM, and a bias terminal BIAS. An operating-point voltage (VOP(1)) for the first differential amplifier OP1 is applied to the first input terminal INP, a voltage at one end of the input capacitor C2 is applied to the second input terminal INM, and a voltage at one end of the bias capacitor C3 is applied to the bias terminal BIAS.
In operation, a difference (VOP(1)xe2x88x92VAIN) between the operation-point voltage (VOP(1)) and the input voltage (VAIN) is sample-held in the input capacitor C2 and also a difference (VBNxe2x88x92VAIN) between a predetermined voltage (VBN) and the input voltage (VAIN) is sample-held in the bias capacitor C3 in a sampling period.
After this, a ramp voltage (VRAMP) is applied to other ends of the input capacitor C2 and the bias capacitor C3 respectively. According to this, a voltage VINM(1) at one end of the input capacitor C2 becomes a sum (VOP(1)xe2x88x92VAIN+VRAMP) of a voltage (VOP(1)xe2x88x92VAIN), which has already been sample-held in the input capacitor C2, and the ramp voltage (VRAMP) applied to the other end. Similarly, the voltage VBIAS at one end of the bias capacitor C3 becomes a sum (VBNxe2x88x92VAIN+VRAMP) of a voltage (VBNxe2x88x92VAIN), which has already been sample-held in the bias capacitor C3, and the ramp voltage (VRAMP) applied to the other end. Since voltages at each one ends of the input capacitor C2 and the bias capacitor C3 are applied to the second input terminal and the bias terminal respectively, voltage values applied to each terminals at this timing are given as follows:
First input terminal INP . . . VOP(1) 
Second input terminal INM . . . VOP(1)xe2x88x92VAIN+VRAMP 
Bias terminal BIAS . . . VBNxe2x88x92VAIN+VRAMP 
In the first differential amplifier OP1, the voltages of the first and second input terminals, i.e., VOP(1) and VOP(1)xe2x88x92VAIN+VRAMP are compared, and its outputs are inverted when these two voltages become equal to each other. The equality of both voltages means VOP(1)=VOP(1)xe2x88x92VAIN+VRAMP and this means VAIN=VRAMP. Therefore, the input voltage (VAIN) and the ramp voltage (VRAMP) are compared in the above operation.
It should be noted that the voltage of the bias terminal is VBIAS=VBNxe2x88x92VAIN+VRAMP, which is smaller than VBN at the period of VRAMP less than VAIN and becomes firstly VBN at the timing of VRAMP=VAIN at which the first differential amplifier OP1 starts to execute the desired comparing operation. Due to the behavior of this VBIAS, merely a small quantity of bias current flows through the first differential amplifier OP1 at the timing of VRAMP less than VAIN, while the bias current value that allows the above desired comparing operation is supplied at the timing of VRAMP=VAIN.
In this manner, since the bias current is not constant but increased gradually in accordance with the ramp voltage, the consumption power in the first differential amplifier OP1 can be reduced.
In this case, a second differential amplifier OP2 may be provided at the later stage of the first differential amplifier OP1. By doing this, the gain of the output can be increased.
In case where the second differential amplifier OP2 is provided in this way, an offset canceling capacitor C4 (C5) may be provided between the first and second differential amplifiers OP1, OP2 and then the difference of the operating-point voltages between the first and second differential amplifiers OP1, OP2 may be held in the offset canceling capacitor. By doing this, deviation of the inverting timing of the output of the second differential amplifier OP2 from the output of the first differential amplifier OP1 due to the difference of the operating-point voltages between two differential amplifiers OP1, OP2 is prevented.
Also, the analog/digital converter of the present invention comprises a counter 5 and a latch circuit 4 for latching a count value of the counter 5 based on an output of the chopper type voltage comparator 1 and outputting the latched count value as an analog/digital-converted value of the input voltage of the comparator 1.
As described above, since the consumption power of the comparator 1 can be reduced, the consumption power of the analog/digital converter using the same can also be reduced.